The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of IC technology, where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, up-to-date developments in IC processing and manufacturing are needed.
FIGS. 1A-C show cross-sectional views of a substrate 102 comprising a frontside 102a and a backside 102b at various stages of fabricating a semiconductor device in a conventional process. FIG. 1A illustrates the structure produced by a conventional isolation fabrication technique that comprises: forming pad oxide layers 112a, 112b over the frontside 102a and the backside 102b of the substrate 102; forming hardmask layers 114a, 114b comprising materials such as silicon nitride over the pad oxide layers 112a, 112b on the frontside 102a and the backside 102b of the substrate 102; forming an opening 122 through the hardmask layer 114a and the pad oxide layer 112a in the frontside 102a of the substrate 102; performing anisotropic etching through the opening 122 to form a trench 124 in the frontside 102a of the substrate 102; filling the trench 124 with a dielectric layer 126 that extends beyond the trench 124 to cover entire surface of the hardmask layer 114a; and performing a chemical mechanical polishing (CMP) to remove the top portion of the dielectric layer 126 above the hardmask layer 114a to expose the hardmask layer 114a on the frontside 102a of the substrate 102, thereby leaving the dielectric layer 126 filling the opening 122 and trench 124.
However, problems arise when subsequently removing the hardmask layer 114a and the pad oxide layer 112a to expose the frontside 102a of the substrate 102, producing the structure shown in FIG. 1C. The hardmask layers 114a, 114b and the pad oxide layers 112a, 112b are removed by two separate wet etching steps. During the first wet etching step using phosphoric acid (H3PO4), the hardmask layers 114a, 114b on the frontside 102a and the backside 102b of the substrate 102 are simultaneously removed, leaving the pad oxide layers 112a, 112b on the frontside 102a and the backside 102b of the substrate 102 as shown in FIG. 1B. Then, a second wet etching step using hydrofluoric (HF) acid simultaneously remove the pad oxide layers 112a, 112b on the frontside 102a and the backside 102b of the substrate 102 to expose portions of the substrate 102 on the frontside 102a and the backside 102b as shown in FIG. 1C.
In some configurations, the exposed portions of the backside 102b of the substrate 102 may provide carrier transportation paths during subsequent plasma-related processes thereby increasing the likelihood of device instability and/or device failure. Accordingly, what is needed is a method for fabricating a semiconductor device having dielectric films on the backside of the substrate from early stage of the device formation.